Friday......

Boy is it hot outside... Glad to get inside, and cooled down.

Haven't made a lot of show able progress today, but I've been going through a lot of FPGA documentation on the Developer Zone on NI's website. Learning a bit more about DMA FIFO memory access, as well as using interrupts. Basically... You compile an FPGA VI to get a specified amount of data from a channel, let's say.. Collect 5 analog samples of a temperature sensor, when it has 5 samples, the FPGA VI, sends it up to the Host VI. Host VI then says, okay, this temperature is out of spec, let's compare it to the last couple values. Okay, it has been out of spec for 6 cycles, therefore, I want to open the cooling valve by Pi()/64 radians, which sends this procedure to a sub-VI that opens the cooling valve a little bit. Once that Sub-VI is done, it goes back to the Host VI, and says, ok, I'm done. The Host VI says, okay, in order for the system to return to steady state from the transient state I just put it in, I need to wait 40 seconds. So... Wait 40 seconds... Then, go back to FPGA VI, and take more samples.. Repeat...

Makes sense to me...

-Kyle